1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure and the like, and a method for manufacturing the same.
2. Description of the Related Art
As a type of non-volatile semiconductor memory devices, the one having a MONOS structure is known.
In the MONOS structure, for example, an ONO film (3-layered film made of an oxide film being an oxidized film-insulating film—a nitride film—an oxide film) is provided between a substrate and a gate electrode. The ONO film can capture electric charges to store them by means of a large number of traps existing in the nitride film in the ONO film, so that when electric charges are taken in and out with respect to the traps, a non-volatile semiconductor memory device can be realized.
As ways for taking such electric charges in and out of the ONO film, there are ways of writing and erasing by taking electrons in and out of the whole surface under the gate electrode with tunneling currents, and ways using hot carriers. The former ways using tunneling currents may increase the number of times of rewriting, and high reliability can be assured. On the other hand, the latter ways of applying hot carriers enable reduction in the operating voltage for writing/erasing data, (whereby manufacturing costs can be reduced), besides enabling high-speed operations.
As a technology for such non-volatile semiconductor memory device having the MONOS structure, there is, for example, that described in Japanese Patent Application Laid-Open (JP-A) No. 2005-64295.
FIGS. 8A and 8B are schematic constitutional diagrams each showing a conventional non-volatile semiconductor memory device having the MONOS structure as described in JP-A No. 2005-64295 and the like wherein FIG. 8A is a schematic sectional view showing the non-volatile semiconductor memory device, and FIG. 8B is an equivalent circuit diagram showing the memory cell in FIG. 8A.
As shown in FIG. 8A, for example, in a P-type silicon substrate 1, a memory cell section 2 for storing information, and a peripheral circuitry section 3 for writing and reading information with respect to the memory cell section 2 are formed. In the memory cell section 2, a plurality of memory cells 10-1, 10-2 and the like are provided, while a plurality of peripheral circuitry transistors (e.g. N-channel type MOS transistor (hereinafter, referred to as “NMOS”) 20 and the like are provided.
The memory cell 10-1 is consisted of a source region 11S made of a high concentration N type (N+ type) impurity layer 11 and a drain region 11D disposed with a predetermined interval, a channel formation region 12 positioned between the source region 11S and the drain region 11D, a source side N− type region 13S made of a low concentration N type (N− type) impurity layer 13 formed between the source region 11S and the channel formation region 12, a drain side N− type region 13D made of the N− type impurity layer 13 formed between the drain region 11D and the channel formation region 12, a gate electrode 15 formed through a gate oxide film 14 on the channel formation region 12, an electric charge accumulation section 16-1 formed on the Source side N− type region 13S and an electric charge accumulation section 16-2 formed on the drain side N− type region 13D.
Each of the electric charge accumulation sections 16-1 and 16-2 is composed of an ONO lamination insulating film having a tunneling oxide film 16a formed on the N− type regions 13S and 13D, the electric charge accumulation layer 16b made of a silicon nitride film formed on the tunneling oxide film 16a, and a NSG (Non-doped SiO2) film 16c formed on the electric charge accumulation layer 16b. 
A periphery circuit NMOS 20 is consisted of the source region 11S and the drain region 11D made of the N+ type impurity layer 11 with a predetermined interval on a surface region of the silicon substrate 11S, the channel formation region 12 positioned between the source region 11S and the drain region 11D, and the gate electrode 15 formed on the channel formation region 12 through the gate oxide film 14. Since the NMOS 20 is manufactured in the same manufacturing process as that of the memory cell 1011, 10-2 and the like, it involves the source side N− type region 13S between the source region 11S and the channel formation region 12, the drain side N− type region 13D formed between the drain region 11D and the channel formation region 12, the electric charge accumulation section 16-1 formed on the source side N− type region 13S, and the electric charge accumulation section 16-2 formed on the drain side N− type region 13D.
An NSG layer 31 is deposited on the memory cells 10-1, 10-2 and the like as well as on the NMOS 20 and the like. In the NSG layer 31, contact holes are provided at the positions corresponding to the source region 11S, the drain region 11D, the gate electrode 15 and the like, each of the contact holes is filled with tungsten (W) 32, and it is electrically connected with a metal wiring 33 on the NSG layer 31.
As shown in FIG. 8B, for example, an equivalent circuit of the memory cell 10-1 involves the NMOS 10A, the source thereof is connected to the source region 11S through a variable resistor of the source side N− type region 13S, while the drain thereof is connected to the drain region 11D through a variable register of the drain side N− type region 11D.
Operation examples (1) to (3) of the memory cell 10-1 will be described below.
In the operations, such a case where recording (writing or erasing) of information (logical value “1” or “0”) and reading with respect to the drain region 11D side of the memory cell 10-1 will be explained as an example. In case of applying the same operation as that described above with respect to the source region 11S side, the same operation may be made by counterchanging power voltage between the source region 11S and the drain region 11D.
(1) Recording of Information (Writing)
An operation for writing information (the logical value “1” or “0”) to the memory cell 10-1 is implemented according to, for example, the following manner. In this case, such a situation that the initial state is considered to be the one where no electric charge is accumulated in the electric charge accumulation sections 16-1 and 16-2 (corresponding to logical value “1”), and logical value “0” is written into the drain region 11D side as information will be described.
In the case when information of logical value “0” is written on the drain region 11D side, a positive voltage (+Vdw) is applied to the drain region 11D, another positive voltage (+Vgw) is applied to the gate electrode 15, and the source region 11S is made to be ground voltage. According to such writing condition as described above, electric field concentrates in the vicinities of the drain side N− type region 13D where an impurity concentration is lower than that of the drain region 11D. Accordingly, generation of hot electrons (which are also referred to as “high energy electrons”) being hot carriers due to ionization by collision converges efficiently in the drain side N− type region 13D. As a result, the hot electrons are selectively injected into the electric charge accumulation section 16-2 from the drain side N− type region 13D over energy barrier of the tunneling oxide film 16a, whereby information can be written.
(2) Reading of Information
Operations for reading the information on the side of the drain region 11D are implemented according to the following manner.
A positive voltage (+Vsr) is applied to the source region 11S, another positive voltage (+Vgr) is applied to the gate electrode 15, and the drain region 11D connected to ground voltage. In the drain region 11D side where logical value “0” is written, since an electric charge (electrons) is accumulated in the electric charge accumulation section 16-2, an ohmic value (resistance) of the drain side N− type region 13D increases. Thus, such a situation where it is difficult for carriers to be supplied to the channel formation region 12 arises so that sufficient electric current stops flowing. On the other hand, in such a situation where the logical value “1” is maintained as it is, i.e. in the initial state, since no electric charge is accumulated in the electric charge accumulation section 16-2, the ohmic value on the drain side N− type region 13D does not vary. As a result, carriers are supplied to the channel formation region 12, whereby sufficient electric current flows. As described above, it can discriminate with certainty which of logical values of either logical value “1” or “0” is written by utilizing differences in values of the electric current flowing through the NMOS 10A.
(3) Recording (erasing) of information
Erasing of information on the drain region 11D side is conducted according to the following manner.
With respect to the drain region 11D side in which a logical value “0” is written, for example, ultraviolet radiation or heat treatment (including allowing standing under high temperature) may be applied for the purpose of neutralizing the electric charge accumulated in the electric charge accumulation section 16-2.
As described above, according to the memory cell 10-1, since it makes possible to concentrate electric charge in the vicinities of the N− type regions 13S and 13D where an impurity concentration is lower than that of the drain region 11S or the drain region 11D to which voltage is applied, it is possible to efficiently concentrate generation of electric charges being hot carriers in the N− type regions 13S and 13D. As a consequence, it is possible to selectively inject the electric charges from the N− type regions 13S and 13D to the electric charge accumulation sections 16-1, and 16-2. Electric charges are accumulated in the electric charge accumulation sections 16-1 and 16-2 to be maintained, whereby information (logical value “0” or “1”) can be efficiently written.
On the other hand, reading of information can be made by utilizing differences in ohmic values of the N− type regions 13S and 13D which vary in response to the presence of the electric charges accumulated by the electric charge accumulation sections 16-1 and 16-2. In other words, when the electric charge accumulation sections 16-1 and 16-2 are charged as a result of writing of information, carriers are difficult to be supplied due to elevation of ohmic values of the N− type regions 13S and 13D so that an electric current flows insufficiently. On the contrary, when the electric charge accumulation sections 16-1 and 16-2 are not charged, ohmic values of the N− type regions 13S and 13D do not vary so that carriers are supplied, whereby a sufficient electric current flows. By applying the difference as mentioned above, the logical value “0” or “1” can be positively discriminated.
As described above, since a non-volatile semiconductor memory device can be realized by a simple structure of a combination of the N− type regions 13S and 13D contributing to efficient writing and reading of information with the electric charge accumulation sections 16-1 and 16-2 which can accumulate electric charges, reduction of the costs can be achieved.
In a conventional method for manufacturing such non-volatile semiconductor memory device, the memory cell section 2 and the periphery circuitry section 3 are manufactured in such a process that these sections 2 and 3 have the same structures for the sake of simplifying the manufacturing steps to reduce masks used for lithography technology and the number of the manufacturing steps therefor.
However, according to a conventional non-volatile semiconductor memory device and the manufacturing method therefor, when electric charges are injected to the memory cell section 2, electric charges are also injected to the periphery circuitry transistors, whereby the hot carrier characteristics become deteriorated, because the memory cell transistors (NMOS 10A) in the memory cell section 2 has the same structures as that of the periphery circuitry transistors (NMOS 20) in the periphery circuitry section 3. For instance, there has been such a problem that the electrons travelling from the source region 11S of the NMOS 20 in the periphery circuitry section 3 in the direction of the drain region 11D cause ionization by collision or avalanche multiplying due to a high electric field in the vicinity of the drain side N− type region 13D, whereby electron-hole pairs are produced. In this case, a part of the pairs of electron and hole (hot ones) is injected to the electric charge accumulation layer 16b on the gate electrode side wall through the tunneling oxide film 16a, and as a result, hot carrier characteristics become deteriorated.